Want to create an interactive transcript for this episode?
Podcast: The Amp Hour Electronics Podcast
Episode: #706 – Leading Edge Analog with Joren Vaes
Description:
Welcome Joren Vaes, design engineer at SOFICS
Simulation is critical when designing analog devices based on a PDK from the fab
Parasitics are significant, especially with new nodes having upwards of 16 metal layers
Chris complained about a class where the professor made them draw planar structures with graph paper with colored pencils
Large fabs on leading edge nodes have 1800 page textbook of rules
Because the constraints get tighter, that book gets longer for each node
2 nm mass production on finfet currently with TSMC
22 was the last classic cmos
Finfet, looks like a devil
‘gate all around’ / nanos...